The present invention relates to an apparatus for generating memory address signals supplied to a display memory for reading out image data recorded in the display memory, especially, an apparatus for generating memory address signals preferable to a panning of a display picture on a display apparatus, where the width of the display memory is larger than the width of the display picture.
In the prior art, for example, as described in Japanese Laid-Open Patent Application No. 57-56885, 1982, an apparatus for generating a memory address signal has a memory address register for memorizing a memory address, a count register, which is cleared at the end of each display line and a pitch register for memorizing an address number in the scanning direction of the display memory. Usually, the memory address signal is calculated by adding the contents of the memory address register and the count register. At the end of each display line, the addition of the contents of the memory address register and the pitch register, is supplied as the memory address signal and stored in the memory address register. In this method, the memory address signal is calculated at each character clock and provided to the display memory.
In general, the display apparatus has come reached to a level of higher resolution. As a result, it has become necessary to make display speed higher. Therefore, according to the above method, in which the calculation is excuted at each character clock, the display speed depends on calculation ability of a processor, so that it is difficult to attain higher display speed. Further, if the processor is fabricated by a complementary metal oxide semiconductor integrated circuit (CMOSIC), the processor operates each character clock, so that it is difficult to reduce power consumption.